In line with the need for low-power design to reduce power consumption while satisfying performance of various applications, there is growing importance of multi-core processors. The world's leading processor manufacturers, such as Intel and AMD (Advanced Micro Devices), have introduced high-performance, low-power multi-core chips, their associated solutions, and products based thereon. In particular, NVIDIA, TI (Texas Instruments), Qualcomm, etc. have released multi-core products for high-performance mobile terminals, presenting road maps for sustainable development thereof.
Meanwhile, there are known low-power techniques for single-core processors. However, in the multi-core environment, there are limits to minimizing power of multi-core systems with the low-power techniques used in the single-core environment. Accordingly, there is a need to modify and compensate the existing low-power techniques used in the single-core environment to be suitable for the multi-core environment.
Multi-core low-power control reduces power consumption by means of estimating a future Central Processing Unit (CPU) usage of a task by analyzing a CPU usage of the task being executed, and adjusting operation or performance of the cores by applying predetermined low-power policies.
This multi-core low-power technique may be roughly classified into Dynamic Power Shutdown (DPS) and Dynamic Voltage Frequency Scaling (DVFS). DPS is a technique of dynamically turning on/off power of cores according to the statuses of cores and the situations of applications, while DVFS is a technique of dynamically adjusting voltages and frequencies of cores according to the core statuses and the application situations. In addition, a technique of adjusting power in combination of these two techniques is called Dynamic Power Management (DPM).
FIG. 1 illustrates a DPS-based power management method, FIG. 2 illustrates a DVFS-based power management method, and FIG. 3 illustrates a DPM-based power management method.
As illustrated in FIG. 1, DPS prevents an unnecessary waste of power by adjusting the number of cores to be turned on, according to the amount of computation. As illustrated in FIG. 2, DVFS reduces the total power consumption of a system by lowering frequencies of cores on the whole. As illustrated in FIG. 3, DPM may maximize low-power control by adjusting both on/off of cores and frequencies of cores according to the amount of computation.
FIG. 4 is a block diagram of a low-power control apparatus for DPM.
As illustrated in FIG. 4, the low-power control apparatus for DPM includes a main controller 410, an Operation System (OS) kernel 420, a CPU usage estimator 430, an execution controller 440, and a policy manager 450.
The main controller 410 controls the CPU usage estimator 430 and the execution controller 440 depending on task status information received from the OS kernel 420. The CPU usage estimator 430 estimates a future CPU usage by monitoring information about a CPU usage during execution of tasks. The policy manager 450 exchanges information about policy control with the CPU usage estimator 430 and establishes a policy for controlling cores. The execution controller 440 directly controls cores according to the information received from the policy manager 450, thereby enabling low-power execution.
Advantageously, this multi-core low-power technique based on the CPU usages may directly check the status of the CPU and control power depending thereon. However, this technique has limits in accurately estimating a change in CPU usage that varies according to applications, and in case of significant error, may degrade performance of the system due to unnecessary core control. Besides, for an application, a change in CPU usage of which is significant, even though the change is accurately estimated, the core control speed may not keep up with the pace of the change in CPU usage, causing possible performance degradation of the system. Furthermore, as cores are frequently controlled depending on the usage change, system overhead may occur unexpectedly, increasing power consumption.
FIG. 5 illustrates a change in CPU usage when a multi-core CPU with 4 ARM11 cores operates on Linux.
In FIG. 5, Scenario A represents a case where an arbitrary application such as a game is run and closed, Scenario B represents a case where a video file is played by a multimedia player, and Scenario C represents a case where an arbitrary application is run and closed, and at the same time, a video file is played by a multimedia player. A CPU usage 1.0 means that the CPU is used 100%. Therefore, it is possible to perform low-power control without performance degradation of the scenarios by enabling one core between 0˜0.25 of the CPU usage, two cores between 0.25˜0.5, three cores between 0.5˜0.75, and four cores between 0.75˜1.00. In FIG. 5, margins at the boundaries are unconsidered.